tw 2871 fisheye distortion correction lsi with built - in image signal processor, motion detector and ddr2 controller fn7989 rev. 1.00 page 1 of 2 december 20, 2012 fn7989 rev. 1.00 december 20, 2012 data sh o r t the TW2871 is a highly integrated fisheye distortion correction lsi with built - in image signal processor, motion detector and ddr2 controller for both network and analog cameras. the TW2871 can pan, tilt and zoom without mechanical moving parts. the tw287 1 supports one hd(1080i) digital output and four sd analog outputs. features host interface ? ? 4 - bit address and 8 - bit parallel data interface ? ? 16 byte slave registers ? ? supports two kinds of extended cycle access (external wait pin and register handshake mode) ? ? auto address increment mode image signal processor ? ? supports bayer format and exte rnal isp input ? ? black level correction ? ? gamma correction ? ? lens shading correction ? ? noise reduction ? ? edge enhancement ? ? wide dynamic range geometric engine ? ? digital pan, tilt and zoom ? ? up to 4 distortion corrected windows and one fisheye window ? ? su pports one hd digital output or 2 sd digital outputs ? ? supports 4 sd analog outputs dsp ? ? harvard architecture (instruction: 24 - bit, data: 24 - bit) ? ? 24 - bit multiplier, 56 - bit alu ? ? 144 instructions including simd and special purpose functions ? ? branch pre dictor for high hit rate ? ? 56 - bit accumulator file ? ? power saving mode achieved by sleep instruction motion detector ? ? detection for motion (md), blind (bd, such as covered by something on purpose) ? ? large input size: 5m (2592x1944) or 8m (3264x2448) cis ? ? detection element 32x24, each mesh can be maskable ? ? support s motion detection speed control and manual strobe ? ? fine adjustments by several thresholds programmed by internal registers ddr2 interface ? ? compatible with jedec ddr2 specification (jesd79 - 2c) ? ? speed bin from 250 to 667mhz at ddr ? ? supports ocd calibration ? ? 64 byte internal buffers , which follow mesi algorithm to utilize high data locality ? ? supports data pre - fetch mechanism to maximize data throughput osd ? ? embedded ram based osd ? ? up to 8 osd windows ? ? up to 256 font s osg ? ? external memory (ddr2) based osg ? ? up to 8 osg windows ? ? support s transparent color applications ? ? security surveillance camera ? ? drive monitor ? ? drive recorder related literature ? TW2871 h ard ware a pp lication note ? TW2871 software application note ? TW2871 programmer note ? TW2871 command manual to request the full datasheet, please visit www.intersil.com/products/TW2871 not recommended for new designs contact our technical support center at 1 - 888 - intersil or www.intersil.com/tsc
TW2871 for additional products, see www.intersil.com/product_tree intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at http://www.intersil.com/en/support/qualandreliability.html intersil products are sold by description only. intersil may modify the circuit design and/or specifications of products at a ny time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information furnished by intersil is believed to be ac curate and reliable. howev er, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other r ights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see http://www.intersil.com fn7989 rev.1.00 page 2 of 2 december 20, 2012 block diagram ahb peripheral (162mhz) host i/f apb i2c gpio ireq cl kgen dsp md ahb2apb isp ge ahb0 (324mhz) ahb2 (324mhz) ahb2ahb ahb2ahb ddr2c/ddr2phy ch0 dvd0 - 15 dvfs, vs, hs isi0 - 15 3 3 3 gpio0 - 2 d0dd 0 - 15 hd0 - 7 dvclk cvbs0, 1, 2, 3 d0da 0 - 12 ha0 - 3 16 d0 d c a s hwaitn hwen hren hcsn sda scl d0dba 0 - 2 d0 dras d0 d csn d0 dwe n d0 odt d0 dclk* d0 d*dqs * d0 ddqm* d0 dcke ddr2c/ddr2phy ch2 d2 dd 0 - 15 d 2 da 0 - 12 d 2dcas d 2 dba 0 - 2 d 2dras d 2d csn d 2dwe n d 2odt d 2dclk* d 2d*dqs * d 2ddqm* d 2dcke isfv islv isclki yuv422 ? copyright intersil americas llc 2012 . all rights reserved. all trademarks and registered trademarks are the prope rty of their respective owners.
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